1. Field of the Invention
The present invention relates to a polycrystalline silicon thin film transistor for a liquid crystal display (LCD) device, and more particularly to a method for forming a polycrystalline silicon layer having a uniform grain distribution.
2. Discussion of the Related Art
In a conventional process for forming a polycrystalline silicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a plasma chemical vapor deposition (PCVD) method or a low pressure chemical vapor deposition (LPCVD) method. When the amorphous silicon layer has a thickness of about 500 Å, it is crystallized into a polycrystalline silicon layer by a crystallization method. The crystallization method is generally either a laser annealing method, a solid phase crystallization (SPC) method or a metal induced crystallization (MIC) method.
In the laser annealing method, an excimer laser beam is applied to an amorphous silicon layer on an insulating substrate to form a polycrystalline silicon layer. In the SPC method, a heat-treatment is applied to an amorphous silicon layer at a high temperature for a time period sufficient to form a polycrystalline silicon layer. In the MIC method, a metal layer is formed on the amorphous silicon layer. The metal layer is used as a crystallization seed in a subsequent heat-treatment to form a polycrystalline silicon layer. In the MIC method, a large-sized glass substrate may be used as the insulating substrate because the heat-treatment in the MIC method is below 600° C.
The laser annealing method has recently become a more prevalent method in forming a polycrystalline silicon layer. The laser annealing method includes forming an amorphous silicon layer on an insulating substrate and then melting the amorphous silicon layer with a laser. Subsequently, the melted amorphous silicon layer is cooled to form a polycrystalline silicon layer.
The SPC method includes forming a buffer layer on a quartz substrate that can withstand temperatures higher than 600° C. (degrees Celsius). The buffer layer prevents contamination from the quartz substrate. Next, an amorphous silicon layer is deposited on the buffer layer and is heated in a furnace at a high temperature for a long time period to form a polycrystalline silicon layer. However, the heat-treatment of the amorphous silicon layer performed at a high temperature for a long time period can not obtain a desirable polycrystalline silicon phase, because the direction of grain growth is irregular. Thus, a gate insulating layer contacting the polycrystalline silicon layer is also irregularly formed when the irregularly formed polycrystalline silicon layer is used in a thin film transistor (TFT). Accordingly, the breakdown voltage of the gate insulating layer decreases. Further, because the grain size of the polycrystalline silicon layer is not uniform, the carrier mobility of the TFT is lowered. Furthermore, a quartz substrate should be used to withstand the high temperatures increasing the substrate cost.
The MIC method forms a polycrystalline layer by using a large-sized glass substrate that has a low cost. However, the quality of the polycrystalline silicon layer is deficient because of the possibility that a metal residue remains in the polycrystalline silicon layer. Accordingly, a field enhanced metal induced crystallization (FE-MIC) method that improves the MIC method is suggested. In the FE-MIC method, after a metal layer is formed on an amorphous silicon layer, a direct current (DC) high voltage is applied to the metal layer to generate heat. Because the metal layer functions as a catalyst, the metal is referred to as a catalyst metal in a MIC method.
FIGS. 1A to 1D are schematic perspective views showing a crystallization process of an amorphous silicon layer using a field enhanced metal induced crystallization method according to the related art.
In FIG. 1A, a buffer layer 12 is formed on a substrate 10 by depositing an insulating layer such as silicon oxide (SiO2). Because the buffer layer 12 prevents the eruption of alkaline materials from the substrate 10, the buffer layer 12 can be used more effectively when the substrate includes the alkaline materials. After amorphous silicon is deposited on the buffer layer 12, an amorphous silicon layer 14 is formed through a dehydrogenation process. The dehydrogenation process for eliminating hydrogen from the amorphous silicon layer 14 may be omitted according to the deposition condition of amorphous silicon.
In FIG. 1B, a catalyst metal 16 such as nickel (Ni) is deposited on the amorphous silicon layer 14.
In FIG. 1C, after the substrate 10 including the amorphous silicon layer 14 is loaded on a heater 18, electrodes 20 contacting two facing ends of the amorphous silicon layer 14 are disposed thereon. The amorphous silicon layer 14 is crystallized by applying a high voltage to the amorphous silicon layer 14 through the electrodes 20.
As shown in FIG. 1D, a polycrystalline silicon layer 24 is obtained through a field enhanced metal induced crystallization (FE-MIC) method illustrated in FIGS. 1A to 1C.
However, because the electrodes are disposed at opposite ends of the amorphous silicon layer, an electric field is generated along a direction. Thus, a current between the electrodes flows along this direction and is non-uniformly distributed. Accordingly, the grain of the polycrystalline silicon layer grows along the direction and the grain distribution of the polycrystalline silicon layer becomes non-uniform. When a thin film transistor is formed by using the polycrystalline silicon layer as an active layer, this non-uniform grain distribution results in decreased performance such as a high OFF current.